Comments on: A/B Test Questions http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/ Higher Computing 2007 - 2008 at Craigmount Wed, 29 Apr 2009 20:59:15 +0000 http://wordpress.com/ hourly 1 By: Steven Donoghue http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-115 Steven Donoghue Sun, 13 Apr 2008 14:34:50 +0000 http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-115 program counter > Memory address register Active the read line Memory address register > Memory data register Add 1 to Program counter Memory data register > Instruction register Decode Instruction register program counter > Memory address register
Active the read line
Memory address register > Memory data register
Add 1 to Program counter
Memory data register > Instruction register
Decode Instruction register

]]> By: Dale http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-28 Dale Fri, 05 Oct 2007 09:21:04 +0000 http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-28 The CPU puts the address of the location that it wants on the Address Bus. The read line of the Control Bus is then activated. The data that comes from the address then travels along the Data Bus. If the CPU is puting data onto RAM it does the following. The location of the address is recieved along the address bus, the write line is then activated. The data that is required then travels along the Data Bus. The CPU puts the address of the location that it wants on the Address Bus. The read line of the Control Bus is then activated. The data that comes from the address then travels along the Data Bus. If the CPU is puting data onto RAM it does the following. The location of the address is recieved along the address bus, the write line is then activated. The data that is required then travels along the Data Bus.

]]> By: craig aka (P'nut) http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-27 craig aka (P'nut) Fri, 05 Oct 2007 09:20:17 +0000 http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-27 the fetch cycle reads instructions from main memory in to the prosessor. the memory addres of the instruction is placed on the address bus. then the read signal is activated on the read line. then the data stored at the addressed memory location is placed on the data bus and transfered to a register which holds it until it is carried out the fetch cycle reads instructions from main memory in to the prosessor. the memory addres of the instruction is placed on the address bus. then the read signal is activated on the read line. then the data stored at the addressed memory location is placed on the data bus and transfered to a register which holds it until it is carried out

]]> By: Natalie http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-26 Natalie Fri, 05 Oct 2007 09:19:56 +0000 http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-26 There is lots of stages in the cycle. To read data from memory, the address has to be placed onto the address bus, which the read line of the control bus is activated. The data is then placed onto the data bus which goes into the CPU. To write data onto the memory the data has to be put onto the data bus, which the address is then placed onto the address bus. The last part of the cycle is when the write line of the control bus is then activated and the data is sent along the data bus to the memory location it is gettin sent to There is lots of stages in the cycle. To read data from memory, the address has to be placed onto the address bus, which the read line of the control bus is activated. The data is then placed onto the data bus which goes into the CPU. To write data onto the memory the data has to be put onto the data bus, which the address is then placed onto the address bus. The last part of the cycle is when the write line of the control bus is then activated and the data is sent along the data bus to the memory location it is gettin sent to

]]> By: Kirsty Henderson http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-25 Kirsty Henderson Fri, 05 Oct 2007 09:19:08 +0000 http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-25 The address the data that is to be read from is placed on the address bus. The read line is then activated on the control bus. The memory then accesses that location and the data in that location is then placed on the data bus. The data is then decoded and executed. The address the data that is to be read from is placed on the address bus. The read line is then activated on the control bus. The memory then accesses that location and the data in that location is then placed on the data bus. The data is then decoded and executed.

]]> By: Gary http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-24 Gary Fri, 05 Oct 2007 09:16:56 +0000 http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-24 Address of memory location is placed on the address bus. The write line is activated on the control bus so that the data is written to the location/ read line is activated so that the memory is taken from the location and put on the data bus Data is placed on the data bus and sent along to the memory location/ data is taken from the memory and placed on the data bus and taken along to the CPU. Address of memory location is placed on the address bus.

The write line is activated on the control bus so that the data is written to the location/ read line is activated so that the memory is taken from the location and put on the data bus

Data is placed on the data bus and sent along to the memory location/ data is taken from the memory and placed on the data bus and taken along to the CPU.

]]> By: Roooooy http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-23 Roooooy Fri, 05 Oct 2007 09:15:56 +0000 http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-23 *A read signal is activiated on the contol bus* :) *A read signal is activiated on the contol bus*
:)

]]> By: Katy http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-22 Katy Fri, 05 Oct 2007 09:15:22 +0000 http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-22 The fetch- execute cycle describes how the processor fetches instructions and then carries them out. It divides into two parts: fetch and execute. Fetch is the part of the cycle that reads the next instruction from main memory into the processor. The memory address of the next instruction is placed in the address bus and then a read signal is activated on the read lines. The data stored at the addressed memory location is placed on the data bus and trasferred to a register which holds it. Execute is the part that interprets and carries out the instructions. The processor interprets the the instruction an d then carries out the instruction. The fetch- execute cycle describes how the processor fetches instructions and then carries them out. It divides into two parts: fetch and execute. Fetch is the part of the cycle that reads the next instruction from main memory into the processor. The memory address of the next instruction is placed in the address bus and then a read signal is activated on the read lines. The data stored at the addressed memory location is placed on the data bus and trasferred to a register which holds it. Execute is the part that interprets and carries out the instructions. The processor interprets the the instruction an d then carries out the instruction.

]]> By: Gaetano http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-21 Gaetano Fri, 05 Oct 2007 09:14:43 +0000 http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-21 The CPU puts the address of the RAM location it wants on the address bus and activates the read line on the control bus. The data is then passed from RAM to the CPU using the data bus. The CPU carries out a process on the data. When the data is passed back to RAM, the address is put on the address bus, the data on the data bus and the write line is activated. The data goes to the appropriate RAM location. The CPU puts the address of the RAM location it wants on the address bus and activates the read line on the control bus. The data is then passed from RAM to the CPU using the data bus. The CPU carries out a process on the data. When the data is passed back to RAM, the address is put on the address bus, the data on the data bus and the write line is activated. The data goes to the appropriate RAM location.

]]> By: Abby http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-20 Abby Fri, 05 Oct 2007 09:14:23 +0000 http://craigmounthighercomputing.wordpress.com/2007/10/04/ab-test-questions/#comment-20 There are many stages to the Fetch-Execute Cycle. In order to read data from memory, the address has to be placed onto the address bus to which the read line of the control bus is activated. After this procedure, the data is placed onto the data bus which goes to the CPU. In order to write data to the memory, the data has to be placed onto the data bus, to which the address is placed onto the address bus. Afterwards, the write line of the control bus is activated and the data is sent along the data bus to the memory location There are many stages to the Fetch-Execute Cycle. In order to read data from memory, the address has to be placed onto the address bus to which the read line of the control bus is activated. After this procedure, the data is placed onto the data bus which goes to the CPU.
In order to write data to the memory, the data has to be placed onto the data bus, to which the address is placed onto the address bus. Afterwards, the write line of the control bus is activated and the data is sent along the data bus to the memory location

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